Input for shift registers

ABSTRACT

A bucket-brigade (charge-transfer-type) shift register wherein an input capacitance is provided substantially equal to the interstage capacitance of the shift-register. The input capacitance is selectively grounded in response to input data signals of one type, after each charge transfer. Subsequently, the input capacitance is recharged to the optimum level for data charge transfer in order to maximize the number of stages possible before a refresh amplifier is needed.

Q United States Patent [1 1 1111 3,801,826

Gorski Apr. 2, 1974 [5 INPUT FOR SHIFT REGISTERS 3,619,642 11 1971 Dunn307 221 1) 5] e r: S n y R. sk h cago In. 3,621,283 11/1971 Teer 307/221D [73} Assignee: Teletype Corporation, Skokie, 111. Primary Ex minr-Jerry D, Craig 22 Filed: y 12 1972 jltttlorteyll 1211 2711, 0! DOSSB;

o n an 15 [21] Appl. No.: 252,696

[57] ABSTRACT US. Cl. 307/221 A buckebbrigade (charge transfer type)shift register 58 Field 61 Search 307/221 c, 221 D, 208; 9 capac'tance Psubstanmily equal to the mterstage capac1tance of the shift- 317/235 Greglster. The input capacitance 1s selectively grounded l ReferencesCited in response to input data signals of one type, after each chargetransfer. Subsequently, the input capaci- UNITED STATES PATENTS tance isrecharged to the optimum level for data 3,660,697 5/1972 Berglund et a1.317/235 charge, transfer in order to maximize the number of g lff gstages possible before a refresh amplifier is needed. er ins 3,576,447 41971 McKenny 307 221 0 16 Cltl t l, 3 l)rawi llg Figure INPUT FOR SHIFTREGISTERS FIELD OF THE INVENTION This invention relates tocharge-transfer-type memory circuits and more particularly to an inputcircuit therefor, which maximizes the number of stages possible betweenrefresh operations.

BACKGROUND OF THE INVENTION Bucket-brigade or charge-transfer-type shiftregister memory circuits are known in the prior art. (Integrated MOS andBipolar Analog Delay Lines using Bucket- Brigade Capacitor Storage, byF. L. .I. Sangster, p. 74, Proce 1970 IEEE Intl. Solid-States CircuitsConferenee). These shift registers transfer data from an input terminalto an output terminal in the form of a charge on a capacitor. Themaximum number of stages possible between an input and an output ofabucket-brigade shift register is limited by two factors. One factor isthe leakage of charge from the interstage capacitance, which tends toattenuate the voltage level of the signal. This phenomenon is alsorelated to cycling speed of the memory since the lower the cycle speed,the longer each hit of data remains on a given capacitor and can leakoff.

The second factor is charge optimization. If charge is transferred froma large capacitor to a smaller capaci tor, this charge will betransferred to the point that the voltages on the two capacitors areequal. At the end of charge transfer, the actual charge on the smallercapacitor is less than the charge on the larger capacitor prior totransfer.

If the charge is now transferred from the smaller capacitor to asignificantly larger capacitor for a given charge transfer, the voltageon the larger capacitor rises less than the voltage falls on the smallercapacitor when they seek an equilibrium at the same voltage. Therefore,mismatching of capacitors in the bucket brigade circuit causesdegradation and attenuation of the charge signal.

In the manufacture of a bucket-brigade shift register,

every effort is made to keep interstage capacitors as equal as possible.These shift registers shown in the prior art contain input circuitswhich are not matched with the initial stages of the shift register,thereby limiting the number of stages possible before the signal must berefreshed. Therefore, an object to the present invention is to providean input circuit to a charge-transfer shift register which will maximizethe number of stages possible at any given clock rate before refreshamplification is necessary.

Another object to the present invention is to match the inputcapacitance of a charge-transfer-type register with the interstagecapacitance of the register.

Still another object of the present invention is to optimize the inputvoltage of the transfer charge in a charge-transfer'type shift registerin order to maximize the number of stages possible before refresh isnecessary. 7

Yet another object of the present invention is to optimize the outputvoltage from a refresh amplifier used in a charge-transfer-type shiftregister.

SUMMARY OF THE INVENTION In accordance with the present invention, aninput memory circuit is selectively discharged in response to receipt ofdata signals and is subsequently partially recharged to an optimumvoltage for charge transfer.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be morereadily understood by reference to the following detailed description,when considered in conjunction with the accompanying drawings, in whichlike reference numbers refer to the same or similar parts throughout theseveral figures and wherein:

FIG. 1 is a schematic diagram of a metal oxide semiconductorfield-effect transistor circuit having input circuits in accordance withone embodiment of the present invention;

FIG. 2( A-I-I) are timing diagrams illustrating various voltage-timerelationships involved in the circuit of FIG. 1; and

FIG. 3 shows an alternate circuit for feeding in data.

DETAILED DESCRIPTION OF THE INVENTION A GENERAL ARRANGEMENT Referring toFIGS. 1 and 2, an input circuit 5 in accordance with the firstembodiment of this invention provides a train of specially regulateddata-input signals to a first stage 6A of a generally prior-known MOSbucket-brigade shift register 6. Each input signal is in sequence, as iscustomary, is a selected one of two binary input voltages representingthe state 1 or 0 of a bit of data, and is derived from a Data Inputsource 7. In a manner to be described, the data input signal is shifted,one position or stage to the right during each complete cycle of twomain clocking pulses 4: and (FIGS. 2A and 2B), and ultimately arrives ata last or nth stage 6N 0f the shift register 6, typically for examplethirty stages or cycles later. One stage or position comprises a pair ofMOS field-effect transistors connected to opposite clock bus conductorsl0 and 12.

From the final stage 6N of the register 6, the data signals are invertedby an inverter circuit 8 and then applied as an input to an inputcircuit 9. The inverter circuit 8 and the input circuit 9, togethercomprise a refresh amplifier which restores the data signals to theiroriginal strength. The refresh amplifier then provides an input signalin accordance with this invention, similar to the input provided by thecircuit 5, to a first stage of a following shift register 6' similar tothe register 6.

The shift register stages and other circuits are operated in succession,as will be described, by two main clocking inputs 1!), and 4%, carriedon clock bus conductors l0 and 12; the data input circuit 5 of FIG. 1 isadditionally triggered by a third clock pulse qb (FIG. 2E) between (11and (b and the refresh amplifier is triggered by a fourth clock pulse@12 (FIG. 2G) occurring between (12 and In general, the shift register 6sequentially transfers the data from circuit 5 one stage to the rightduring each cycle, by either transferring or not transferring a portionof a capacitor charge to the left from one stage to the next precedingstage, depending on the value of the data bit at the. preceding stage.In the example described, a 1" bit causes leftward charge transfer alongthe register 6, while a bit precludes any effective charge transfer.

Whenever necessitated by charge transfer, a fresh reference charge isimpressed on the final stage 6N by a charge-input circuit 13, at thestart of each cycle (4),). This charge is then transmitted or nottransmitted to the left during following cycles, depending on the valuesof the incoming bits, and eventually reaches the input circuit 5.Finally, the transferred charge is selectively discharged to ground atthe data input source 7, whenever the next input bit is of onedesignated binary state (a binary l in the example described).

With this general background in mind, the specific operation of theshift register 6 will next be described, followed by a description ofthe input circuit 5, the charge refresh amplifier 9, and finally thealternate input circuit shown in FIG. 3.

B BUCKET-BRIGADE SHIFT REGISTER 6 The ensuing description will followthe selective transfer of charge from the charge-input circuit 13 andthe final stage 6N of the register 6 to the left in FIG. 1,

toward the data-input circuit 5. At the start of each cycle (clock pulse4),), the clock conductor 10, which is normally at ground potential,experiences a cyclical excursion from ground potential to some negativevoltage, volts in the specific example, in a well-known fashion. On eachnegative excursion of the 4), clock pulse, an input field-effecttransistor 14, which has its gate electrode and one of its controlledelectrodes connected to the clock conductor 10, may become conductiveand charge a pair of interstage capacitors 20 and 22 which are connectedtogether at a terminal referred as a node 24.

As will be described, the transistor 14 turns ON during 4) to charge thecapacitors 20 and 22 whenever a l data signal was previously present atthe node 24. As illustrated, the capacitor 20 has one electrodeconnected to the node 24 and the other electrode connected to ground,while the capacitor 22 is connected between the node 24 and the 4) clockconductor 12. The capacitor pair 20-22 is typical of interstagecapacitor pairs provided throughout the shift-register circuit.

The present circuit is intended as an integrated circuit to be formed ona single metal-oxide semiconductor (MOS) substrate, wafer, or chip.Therefore, the capacitors can be either intrinsic to the formation ofother portions of the circuit or can be separately formed in the chipduring its manufacture. For example, the capacitor 20 can be an enlargeddiffusion on the MOS substrate, and the capacitor 22 canbe an enlargedgate overlap region of an MOS field-effect transistor.

When the transistor 14 turns ON during 4),, the capacitors 20 and 22 arecharged to the negative voltage of the clock conductor 10, minus asubstantial threshold voltage of the transistor 14. The magnitude ofthis threshold voltage is dependent upon many factors including themanner in which the chip was manufactured and the voltage differencebetween the source electrode of the field-effect transistor 14 and thesubstrate usually the most positive voltage used with the circuit. Thisthreshold voltage must exist between the source and gate electrodes ofthe field-effect transistor for it to be in the ON condition. For easeof understanding, the threshold voltage is taken here as-being aconstant of about six volts in this example. Therefore, the field-effecttransistor 14, whenever actuated during 4),, charges the node 24 toapproximately -l4 volts during each 4), clock pulse, in a typicalexample as indicated by the line A in FIG. 2C.

After the 4) clock pulse, the clock bus conductor 10 returns to groundvoltage, the input transistor 14 turns OFF and the node 24 is thereafterisolated from the 4) conductor 10 until the next 4) pulse. Thus, theinput circuit 13 selectively impresses a reference charge of 14 volts onthe node 24 during the 4), pulse whenever a l was previously present atthat node. As will be discussed, if a 0 was previously present at thenode 24, a previously applied reference charge of -14 volts remains atthe node 24. In any event, at the end of each 4) pulse, the node 24 isinvariably charged to the reference voltage ofl4 volts. The node 24 maybe considered as the output end of the final shift register stage 6N,and is also the starting point for the selective transfer of charge tothe left, depending on value of an incoming data bit.

When the 4) negative clock pulse occurs on the bus 12 some time later(FIG. 2B), the node 24 is made still more negative by the coupling ofthe capacitor 22 (line B in FIG. 2C). It can be seen that, if thecapacitors 20 and 22 are of approximately equal capacitance, thecoupling of the capacitor 22 causes the node 24 to become more negativeby an amount equal to approximately percent (-10 volts) of the 4), clockpulse voltage (also -20 volts in the example). Therefore, at thebeginning of the 4), clock pulse, the node 24 is invariably charged toapproximately 24 volts. This temporary extra charge from -14 to 24 voltsby the capacitive coupling with 4 represents the driving force forselective charge transfer during (1) if the adjacent, preceding signalis a I as will be explained hereafter.

The negative 4) clock pulse also may or may not turn ON a field-effecttransistor 26, depending on the state of an adjacent, preceding datasignal. The transistor 26 has a gate 28 connected to the (1) clock busconductor 12, and also a drain 30 and a source 32 connected to the node24 and an adjacent, preceding node 34, respectively. The node 34 isconnected to two interstage capacitors 36 and 38, similar to 20 and 22.As will be explained subsequently, the node 34 at the time of the 4)pulse is at either one of two possible states: (a) a high negativevoltage (the negative clock voltage minus the threshold voltage, or -14volts in the example), representing a binary 0; or (b) a low negativevoltage approximately 4 volts in the preferred example), representing abinary l at the adjacent, preceding node 34.

Assuming first that the node 34 is at the high negative voltagerepresenting a binary 0 (-14 volts) line C in FIG. 2D the voltagedifference of 6 volts between the source 32 (-14 volts) and the gate 28(-20 volts) of the field-effect transistor 26 will not be sufficient(more than 6 volts needed) to render the field-effect transistor 26conductive. Therefore, no current flows through the field-effecttransistor 26, and the voltages at the nodes 34 and 24 do not changeduring the 4) pulse, but remain at -14 and 24 volts, respectively. Afterthe 4), pulse, the coupling charge applied by the capacitor 22 to thenode 24 is removed and the node 24 returns to its previous state of 14volts (line D in FIG. 2C). In this manner, a binary O has now beentransferred from node 34 to node 24, meaning simply that the node 24 didnot discharge a significant portion of its charge to the preceding node34 during and that it remains at 14 volts after This state is now thehigh negative charge at the node 24, indicating a 0 output from theshift register 6, the further handling of which is discussed in SectionD of this specification.

Conversely, if the node 34 is at the low negative voltage at the startof (4 volts, representing a binary 1 as depicted by line E in FIG. 2Dduring a second cycle illustrated), the negative clock voltage volts)applied to the gate 28 of the field-effect transistor 26 is sufficientlymore negative than the voltage (-4 volts) applied to the source 32 torender the field-effect transistor 26 conductive, the threshold voltagedifference being approximately 6 volts. At the beginning of b the chargeat the node 24 is again boosted to 24 volts through the coupling ofcapacitor 22 to the bus 12, as indicated by the negative peak B in FIG.2C. Current then flows from the more positive node 34 (4 volts), throughthe source 32 of the field-effect transistor 26, to the drain of thefield effect transistor 26, and to the node 24 (24 volts).Simultaneously, this same current charges the capacitors 36 and 38 morenegatively.

Stated in terms of charge transfer, the capacitors 22 and 20 partiallydischarge through the ON transistor 26, as indicated by line F in FIG.2C, from the peak voltage B, to increase the negative charge on thecapacitors 36 and 38, as indicated by line G in FIG. 2D.

This charge transfer or dumping from node 24 (initially at 24 volts) tonode 34 (initially at 4 volts) is designed to continue until thevoltages at the nodes 24 and 34 reach equilibrium at the same voltage(l4 volts in the example). In addition, the charge transfer would stopearlier if the node 34 reached the negative clock voltage minus thethreshold voltage prior to equalization since, if the node 34 reachedapproximately the negative clock voltage minus the threshold voltagebefore equilibrium occurred, the field-effect transistor 26 would turnOFF and the charge dumping would stop. However, the circuit componentsand values are designed and chosen such that equilibrium occurs at 14volts, which is substantially the point when the field-effect transistor26 turns OFF. Therefore, the node 34 will always be at -l4 volts afterthe transfer of a binary 1" to the node 24, as indicated by line H inFIG. 2D.

As previously described, the final voltage at node 34 after (1) when a 0is transferred (no charge transfer), is also 14 volts, as indicated byline C in FIG. 2D. Thus, the voltage at node 34 after (lines C or H) isinvariably 14 volts, regardless of whether a 0 or a 1" was transferredto the node 24 during This is the same reference voltage to which node24 was invariably charged prior to and (when later boosted to 24 volts)constitutes the driving force for further selective charge transfer tothe left during the next occurrence of the (I), clock pulse.

At the end of the 4: clock pulse, the bus conductor 12 returns to groundor zero voltage. The coupling of the capacitor 22 then causes the node24 to assume a voltage (4 volts) that is ten volts less in magnitudethan the equilibrium voltage (l4 volts), as depicted by line I in FIG.2C. This is also the low negative voltage, previously described asindicating a 1". Therefore. the transfer of charge to the left throughthe field-effect transistor 26 during the (b clock pulse effectivelytransfers the binary l condition (4 volts) one cell to the right, fromthe node 34 to the node 24 at the end of the clock pulse.

As will be described in Part D hereof, this binary output from the shiftregister 6 is later (after 4);) inverted by the circuit 8 and serves asthe input to the refresh amplifier 9. However, if a 1 output of 4 voltsis present at the node 24 after 4J the input transistor 14 will turn ONduring the next d), clock pulse, as previously described, to rechargethe node 24 to the reference voltage of l4 volts in preparation for thenext data-transfer cycle to node 24 (the next incidence of This isindicated by the line J at the right of FIG. 2C, which corresponds tothe line A (previously described) at the left of FIG. 2C. Conversely, ifa 0 was transferred, the node 24 remains at -l4 volts after 5 (no chargetransfer, as indicated by line K in FIG. 2C), the node 14 remains at thereference voltage". Also, as previously mentioned, the input transistor14 does not turn ON in this case of a 0 transfer during the following(1), pulse, since insufficient gate-to-source voltage difference isavailable whenever a 0 is transferred.

The transistor 26 constitutes one cell or half of the shift registerstage 6N, being triggered during to transfer the data signal at the node34 to the following node 24. The stage 6N also includes a field-effecttransistor 40, which operates similarly to the transistor 26, but during(1),, to transfer an incoming data signal from a preceding node to thenode 34. Since many stages exist between the input and the output of theshift register 6, the dashed lines 42 are used to represent theseintervening stages between the first stage 6A and the final stage 6N. Anode 44 at the output end of the first stage 6A may, for purposes ofillustration, be assumed to be connected directly to the source 46 ofthe fieldeffect transistor 40 across the dashed lines 42.

During the succeeding clock pulse, the negative clock pulse (20 volts)appearing on the bus conductor 10 attempts to render the field-effecttransistor 40 conductive. As shown above in connection with the binary1" and 0 illustrations, the node 34 is always at the reference voltageof-l4 volts (lines C or H in FIG. 2D) at the end of the clock pulse andremains at that voltage until the beginning of the next 4), clock pulse.However, the node 44 can be at either the high negative voltage (14volts, binary 0) or at the low or negligible negative voltage (4 volts,binary 1 in accordance with the charge on the two interstage capacitors48 and 50 connected to the node 44.

The selective transfer of charge during the d), clock pulse between thenodes 34 and 44 through the fieldeffect transistor 40 is identical tothe transfer of charge during the clock pulse by the field-effecttransistor 26 between the nodes 34 and 24. Thus, at the beginning of thed), clock pulse, the charge at node 34 is invariably boosted to 24 voltsby the coupling capacitor 38 (linkes K or K in FIG. 2D) and may or maynot discharge partially to the node 44, depending on the incoming datasignal. Therefore, at the end of the 41, clock pulse, the node 44 isinvariably charged to substantially the reference voltage of -14 volts,and the node 34 carries a charge representative of the binaryinformation previously contained at the node 44, either 4 volts (line E)or l4 volts (line C).

In this manner, it can be seen that the selective transfer of chargefrom the right to the left in the bucketbrigade shift registerrepresents the transfer of information from left to right in the bucketbrigade. Consequently, the information contained on each nodecorresponding to the node 44 is transferred during the (I), clock pulseto the succeeding node corresponding to the node 34. Similarly, duringthe (b clock pulse, the information contained on each node correspondingto the node 34 is transferred to a following node corresponding to thenode 24.

The initial stage 6A functions in the identical way to transfer inputdata applied by the input circuit 5, in a specially regulated mannerdescribed in the next selection, to a node 54 comprising the input tothe shift register 6. The input node 54 is connected to the source 56 ofa first stage transistor 58, which may operate during the (b, clockpulse in the same way as the transistor 40 to transfer the input dataone position to the right toward the final stage 6N.

C INPUT CIRCUIT In order to provide data to the input of thebucketbrigade shift register 6, two capacitors 60 and 62 are connectedto the input node 54 in exactly the same manner as the interstagecapacitors 22 and are connected to the node 24. Also, the capacitor 60has a capacitance that is equal to or preferably very slightly less thanthe capacitance of the capacitor 48; and the capacitance of thecapacitor 62 is equal to or preferably very slightly less than the valueof the capacitor 50.

In the transfer of charge from right to left the shift register, thereis a small charge leakage which causes the charge voltages to dropslightly. To compensate for this leakage, it is desirable to increaseslightly (about 5 percent) the capacitance at the last node 24 and todecrease slightly (about 5 percent) the capacitance at the input node54. This increase in the capacitance at the node 24 will not alter the 0state voltage on the node 34 after each d), clock pulse but the node 34will be at the same voltage as the clock voltage less the thresholdvoltage (i.e., l4 volts) because the field-effect transistor 26 cuts offat that voltage. However, if the capacitance of the node 24 is slightlylarger, the node 34 will be assured of receiving its full charge. By thetime this charge reaches the node 44, leakage has reduced its voltagemagnitude to somewhat less than l4 volts. Consequently, the charge, whentransferred to the slightly-Iowar-capacitance node 54 will be morenearly equal to l4 volts.

These slight differences in the capacitances of the nodes 24 and 54 arebuilt into the shift register in manufacture. Theentire shift registeris made as an integrated circuit on a single metal-oxidesemiconductor(MOS) chip. The grounded capacitors 20 and 36 are the intrinsiccapacitances resulting from the drain and source diffusions of thefield-effect transistors (FETs) 26 and 40, respectively. In order toincrease or decrease these capacitances, the diffusion areas of thedrains of the associated FETs are increased or decreased.

Similarly, the capacitors 22 and 38 are the intrinsic gate-to-draincapacitances formed by the overlap of the gate electrode and the draindiffusion, with the thinoxide gate dielectric therebetween. The valuesof capacitance of the capacitors 22 and 38 are thus controlled bycontrolling the area of overlap between the drain diffusions and gateelectrodes of the FETs 26 and 40.

In a bucket-brigade shift register such as that described herein, manyintrinsic capacitances exist in addition to those shown in theaccompanying drawing. These stray capacitances are undesired andunavoidable, but are minimized in manufacture.

Except for the abovementioned preferred 5 percent lower value ofcapacitance at the node 54, it is desired to make the input stage 5 asmuch as possible like the other stages of the shift register. Suchduplication causes the input stage 5 to contain as nearly as possibleall of the other, stray intrinsic capacitances found in a shift registerstage. These similarities further enhance the matching of the inputcharacteristics to the characteristics of each shift register stage soas to optimize charge transfer.

The drain 66 of an input field-effect transistor 64 is also' connectedto the node 54. The source 68 of the field-effect transistor 64 isconnected to an input terminal 70, and the gate of the field-effecttransistor 64 is connected to another input terminal 72. After the endof the (I), clock pulse and before the beginning of the next (b clockpulse, the node 54 can be selectively discharged to ground potentialthrough the field-effect transistor 64, in order to provide a 1 datainput to the shift register in the example given.

In the first, and simplest embodiment of the input circuit shown in FIG.1, the source 68 of the field-effect transistor 64 is connected via theinput terminal 70 of the data input source 7. The data source 7 suppliesa voltage that is substantially zero or ground voltage in order torepresent a binary 1". To represent a binary 0, the data source 7supplies a voltage which should be at least as negative as the negativeclock pulse voltage less a threshold voltage (i.e., l4 volts). In apractical application of the shift register circuit, the data inputsource 7 might comprise the output of another shift register. The outputof the shift register will subsequently be shown to be either l4 volts(clock voltage less a threshold voltage) or ground voltage (rather than4 volts, as would otherwise be expected).

The gate terminal 72, in this embodiment, is connected to the thirdclock pulse signal which provides a negative pulse of 20 volts in theexample, only after the end of the (b, clock pulse and prior to thebeginning of the (1) clock pulse as illustrated in FIG. 2E. Therefore,ifa binary 1 is to be inserted at the input node 54, substantiallyground voltage is applied to the terminal 70 and the negative clockpulse is applied to the terminal 72, causing a substantial negativegate-tosource voltage to be applied to the field-effect transistor 64.This causes the field-effect transistor 64 to become conductive and todischarge the capacitors 60 and 62 of the node 54 to the ground voltageof the terminal 70, as depicted by the line L in the right-hand orsecond cycle portion of FIG. 2F. Prior to (1) the node 54 is invariablyat the 0 state or reference voltage of l4 volts for reasons similar tothe operation of the nodes 34 and 44 as will be explained hereafter.

Alternatively, if the input terminal 70 is held at a high negativevoltage, at least as negative as the clock voltage less a threshold(binary 0), the field-effect transistor 64 is held OFF by a negligibleor insufficient voltage difference between its source and gate, aspreviously discussed with respect to the transistors 14 and 26.Therefore, the node 54 is not discharged, but remains at substantially-l 4 volts after 1: as indicated by line M in the left-hand portion ofFIG. 2F.

Assuming that the node 54 has been discharged to ground potential, inorder to insert a binary l at the node 54 (line L) of FIG. 2F, theground voltage on the node 54 is not the most desirable voltage forcharge transfer.

It has been shown that a charge of approximately -14 volts is insertedby the FET 14 into the node 24 and is transferred to the left in theshift register. A 1" state signal is represented by a charge at only -4volts and is transferred to the right by displacing a charge at -14volts to the left. If a ground or zero-volt signal were present at agiven node, the following node would still be at -14 before transfer.After charge transfer, the given node would be at only -12 and thefollowing node would-be at -2 volts. After several successive transfers,such voltage variations can become large enough to cause uncertainty asto the binary state represented. Therefore, -4 volts is the optimumvoltage for transferring a 1 state signal in the present example, ratherthan ground or zero voltage.

In another example of optimum charge transfer voltage assume that thecapacitors 60 and 62, 38 and 36, and 22 and 20 are approximately allequal. If the clock voltage is now assumed to be -16 volts and asix-volt threshold is assumed, the FET 14 charges the node 24 toapproximately volts. The coupling of the capacitor 22 raises the node 24to -18 volts at the start of the (b clock pulse. If the node 34 is atground or zero voltage, current will flow through the FET 26 until thenodes 24 and 34 reach an equilibrium at -9 volts. After the end of thed), clock pulse, the coupling of the capacitor 22 changes the node 24 to-l volt rather than the original ground voltage. Similarly the node 34is only at 9 volts rather than the -10 volts to which the node 24 hadexisted prior to the pulse.

However, if the node 34 had been at -2 volts prior to the 11);. clockpulse, the nodes 34 and 24 would have reached an equilibrium at -10volts. The coupling of the capacitor 22 would then leave the node 24 at2 volts after the clock pulse, and the node 34 would be left at -10volts. Consequently, with the -16 volt clock pulse, as set forth above,-2 volts is the optimum binary l voltage for the charge transfer.

It can be induced from these examples that the binary 0 should berepresented by the clock voltage less a threshold. The binary l shouldthen be represented by a voltage equal to the binary 0" voltage less aproportion of the clock voltage. That proportion is the ratio of theclock-coupling capacitance (22, 38, or 60) to the total nodecapacitance. In the examples explained herein, this proportion isassumed to be approximately one-half.

In order to optimally adjust the data input charge in accordance withthe invention, a field-effect transistor 80 has its source electrode 82connected to the node 54. The drain 84 and gate 86 of the field-effecttransistor 80 are both connected to the (b clock bus conductor 12.Therefore, after the termination of the 4: clock pulse, the (b clockpulse begins and attempts to turn on the field-effect transistor 80.

If the node 54 was required during (153 to retain its charge of -14volts (line M of FIG. 2F), indicating that a binary 0 is to be inserted,the field-effect transistor will remain OFF for lack of a sufficientthreshold voltage difference as previously described. The voltage atnode 54 will temporarily increase to -24 volts during due to thecoupling of the capacitor 60 (line N), but will then return to -14 voltsafter (line 0) and comprises the binary 0 input previously described.

Conversely, if the node 54 has been discharged to substantially groundvoltage during 4);, (line L of FIG. 2F), an adequate source-to-gatevoltage difference exists on the field-effect transistor 80 to cause itto become conductive, even after the coupling of the capacitor 60 booststhe node 54 from ground to approximately -10 volts (line P, FIG. 2F).The field-effect transistor 80 then charges the node 54 from -10 voltsto -14 volts (substantially the voltage of the negative clock less thethreshold voltage), as indicated by line Q in FIG. 2F. After thetermination of the (b clock pulse, the clock bus 12 returns to groundvoltage. The coupling of the capacitor 60 causes the node 54 then toassume a voltage that is ten volts (one-half of the clock voltage of -20volts) less than the negative clock voltage minus the threshold voltage,as indicated by the line R in FIG. 2F. This is the ideal, optimumvoltage (4 volts) for charge transfer through the bucket brigade andconstitutes the binary 1 input previously described.

Such optimum charge characteristics are obtained by having thecapacitance of the node 54 substantially equal to or very slightly lessthan the capacitance of the other nodes of the bucket-brigade shiftregister as mentioned previously. By this technique, the optimum chargetransfer voltage is achieved by discharging the node 54 excessivelythrough the input field-effect transistor 64, and then adjusting thecharge of the node 54 back up to the optimum voltage for chargetransfer.

In the operation of the input circuit, to insert a binary 1 data bitinto the shift register 6, the node 54 is first grounded by thefield-effect transistor 64 during 41 (line L of FIG. 2F). The next clockpulse is coupled through the capacitor 60 to make the voltage of thenode54 ten volts more negative (line P). The fieldeffect transistor 80then turns ON and conducts current so as to correct the voltage of thenode 54 to -14 volts (line Q). At the end of the qb clock pulse, thecoupling of the capacitor 60 makes the node 54 ten volts more positive(to -4 volts), line R, and the binary l input is now optimally availableto the source 56 of the first transistor 58 of the shift register.

The subsequent clock pulse turns ON the fieldeffect transistor 58 andcouples through an interstage capacitor 87 (similar to the capacitors 38and 22) to make the following node 88 ten volts more negative (to -24volts) as previously described with respect to the node 24. Currentflows through the field-effect transistor 58, which charges the node 54to -14 volts (line S of FIG. 2F) and discharges the node 88 to -14volts, as previously described with respect to nodes 24 and 34. At theend of the q), clock pulse, when the bus 10 returns to ground voltage,the node 88 changes to 4 volts as previously described with respect tothe node 24 (similar to line E in FIG. 2D). This completes the transferof the binary 1 from the input node 54 to the first intermediate node88, from which point it is transferred to the following node 44 duringthe next (152 pulse in the manner previously described. This alsoexplains how the node 54 again arrives at the -14 volt reference voltageafter qfi in the case of a l input (line M and line S in FIG. 2F).

After the end of the (b, clock pulse, the field-effect transistor 64again attempts to discharge the node 54 to ground voltage during thenext pulse. Assuming that the field-effect transistor 64 this time hasentered a binary into the node 54, by failing to discharge the node 54(line M at the left of FIG. 2F), the next (1) clock pulse is coupledthrough the capacitor 60 to the node 54 and changes the node 54 to 24volts (line N). Consequently, no current flows through the field-effecttransistor 80 during Q5 and when the (b clock bus 12 returns to groundvoltage, the coupling of the capacitor 60 changes the node 54 back to 14volts, to represent a binary 0 (line 0, FIG. 2F).

During the next (it, clock pulse, this 0 (-14 volts) at the node 54 istransferred to the following node 88 in the manner previously described,by failing to turn on the following transistor 58 and thus failing topartially discharge the node 88 to the node 54. The fieldeffecttransistor 58 does not conduct any substantial amount of current in thiscase; because, there is only a difference of six volts (barely athreshold) between the source electrode 56 and the gate electrode of thefieldeffect transistor 58, which is connected to the clock bus 10. Atthe end of the (b, clock pulse, the coupling of the capacitor 87 changesthe node 88 back to l4 volts to represent a binary 0, which isthereafter transferred to the node 44 during the next pulse in the usualmanner.

Thus, the progress of binary 1 and 0 signals has been shown in thisSection from the field-effect transistor 64 to the node 54, thence tothe nodes 88 and 44 of the shift register 6, while the preceding SectionB described the transfer along the shift register to the output node 24.The following Section D covers the further processing of the datasignals from the node 24 by the refresh amplifier 9.

D CHARGE REFRESH AMPLIFIER 9 As previously indicated, the chargetransferred from node to node tends to'leak off and otherwise diminishas the number of shift register stages. Therefore, it is necessaryperiodically to refresh the charge, or restore it to its originalstrength; for example, after thirty stages of a register such asillustrated. This is accomplished by a charge-refresh circuit 9, whichconsists substantially of a regulated-charge input circuit in accordancewith this invention, and an output circuit 8.

Output from the bucket-brigate shift register 6 is normally obtainedfrom the node 24 after the 4: clock pulse and before the next (I), clockpulse. During the clock pulse, the field-effect transistor 26selectively may partially discharge the capacitors and 22 at the node 24in accordance with the prior, datarepresenting charge condition of thecapacitors 36 and 38 at the node 34, as previously described in SectionB. To review that operation, the charge at node 24 after (1) is either14 volts for a binary 0 output (line D in FIG. 2C), or 4 volts for abinary 1" output (line I in FIG. 2C). After the (b clock pulse, thecharge on the node 24 is available to control the gate electrode 114 ofthe field-effect transistor 116 of the inverter circuit 8.

During each ((1 clock pulse, a field-effect transistor 118 assures thatan output capacitor 120 is fully charged to substantially the negativeclock voltage less the threshold voltage, to -l4 volts in the examplegiven.

The presence of a negligible or substantially ground voltage (-4 voltsin the example, indicating binary l) at the node 24 after thetermination of the (b clock pulse (line I in FIG. 2C) keeps thefield-effect transistor 116 turned OFF, so that the output capacitor 120remains charged. A continuing charged state of the capacitor 120 after42 thereby indicates that a binary 1 is present on the node 24, forgenerating one type of input to the next bucket-brigade shift register6' at the right of FIG. 1.

On the other hand, if the node 24 is charged to approximately thenegative clock voltage less the threshold voltage (approximately -l4volts, representing a binary 0 condition), as indicated by line D inFIG. 2C, the field-effect transistor 116 remains ON after thetermination of the (b clock pulse, and as long thereafter as thesubstantial negative voltage is present on the node 24 (until the next 1signal arrives at the node 24). When the field-effect transistor 116 isON, it discharges the capacitor 120 and anything else connected to it tothe now grounded clock bus 12. Note that this is similar to thegrounding of the node 54 in the input circuit 5, through the transistor64, whenever a binary l is to be inserted into the shift register 6.

Some time after the end of the ((9 clock pulse, but before the beginningof the next clock pulse, the (I), clock pulse (FIG. 2G) is applied to aclock terminal 124 which is connected to the gate electrode 126 of afield-effect transistor 128. The drain 130 of the fieldeffect transistor128 is connected to an input node 132 of the next bucket-brigade shiftregister 6. The input node 132 corresponds approximately to the inputnode 54.

During the (b clock pulse, the capacitors 134 and 136 of the input node132 are selectively discharged to the grounded (12 clock conductor 12 bythe selectively conductive field-effect transistor 116 whenever thattransistor is ON, indicating a 0 or 14 volt output at node 24. This isindicated by line T in FIG. 2H, which depicts the charge at node 132 atvarious times for both 0 and 1 transfer. Prior to the 4),, clock pulse,the capacitors 134 and 136 of the node 132 are invariably charged tothereference charge ofl4 volts (the negative clock voltage minus thefield-effect transistor threshold voltage), in a manner describedhereafter. Therefore, if the node 24 is at 14 volts (binary 0), itmaintains the field-effect transistor 116 ON and the node 132 isselectively discharged to ground (line T) through the field-effecttransistors 128 and 116 during the duration of the d), clock pulseapplied to the clock terminal 124. However, if the node 24 is at 4 volts(binary l), the field-effect transistor 116 is in the OFF condition, andthe node 132 remains at 14 volts during 42., (line U in FIG. 2H).

In this way, a substantial, negatively-charged condition of the node 24results in a discharged or groundvoltage condition of the node 132. Asubstantially discharged, or 4 volts, condition of the node 24 resultsin a negatively-charged condition of the node 132. Thus, the data signalat node 24 is inverted by the transistors 116 and 118 and capacitor 120of the inverter circuit 8, and the inverted signal is available at thenode 132 after (15 After the termination of the 41,, clock pulse, thefield'effect transistor 128 is turned OFF,

thereby decoupling the node 132 from the field-effect transistor 1 16.

After the termination of the ,,clock pulse, the next 41), clock pulseattempts to turn ON a field-effect transistor 140 (analogous to thefield-effect transistor 80). Simultaneously, an additional charge of 10volts (approximately half of the d), clock voltage) is applied to thenode 132 through the coupling of the capacitor 136, similar to theaction of the coupling capacitor 60 described in Section C. If the node132 has previously remained charged to l4 volts as a result of adischarged ground-voltage condition of the node 24 (line U of FIG. 2H),the transistor 140 remains OFF through lack of sufficient gate-to-sourcevoltage difference.

In this situation, the node 132 is additionally charged to 24 voltsduring 4), (line V of FIG. 2H) due to the coupling of the capacitor 136,and then reverts to its previous charge of l4 volts after (line W). Inthis manner, it is seen that the node 132 retains the voltage of -14volts after 4), whenever a l was transferred from the last stage 6N ofthe previous shift register 6.

Conversely, if the node 132 has been discharged to substantially groundby a sutstantial negative voltage at the node 24 prior to the (b, clockpulse, the coupling capacitor 136 first increases the charge to 10 volts(line X of FIG. 2H), and the field-effect transistor 140 turns ON tofurther charge the node 132 to the clock pulse voltage minus thethreshold voltage, or approximately l4 volts (line Y). After thetermination of the d), clock pulse, the coupling of the capacitor 136 tothe 15, clock bus 10 reduces the magnitude of the negative voltage ofthe node 132 to the negligible, negative voltage (-4 volts) optimum forthe charge transfer through the remainder of the bucket-brigade, asindicated by line Z.

In this manner, the transistor 140 and capacitor 136 function toselectively charge the input node 132 of the second shift register 6 tothe optimum low negative voltage of approximately 4 volts whenever abinary was transferred from the preceding shift register 6. It should benoted that this optimum charge adjustment by the transistor 140 andcapacitor 136 is precisely the same as that provided by the inputtransistor 80 and coupling capacitor 60. Thus, the input data signals,initially provided by the input circuit 5, have been regenerated andprecisely reconstituted by the refresh amplifier 9, only in invertedsense such that the optimum low negative voltage of 4 volts at node 132(line Z) now indicates a binary 0" and the high negative voltage of-l4volts (line W) indicates binary 1. This inversion (caused by theoperation of the transistor 116) is of minimal practical significance inthe operation of a shift register system. If an even number of shiftregisters, each having one inverter output stage, are employed togetherin a long series of shift registers, each data bit is then inverted aneven number of times and is delivered at the final output stage in itsoriginal binary sense. If an odd number of shift registers are used,each with one inverter, then the inverse of the desired output must bedelivered to the input of the long series of shift registers.

Once the data bit (or its inverse) is present as the state of the chargeat the node 132, the next 42 clock pulse causes a selective chargetransfer from a following node 144 (comprising the first cell of thefollowing register 6') through a field-effect transistor 146 to the node132 in exactly the same way as in the preceding shift register 6. Thetransistor 146 and a pair of capacitors 148 and 150, for example,correspond precisely to the transistor 26 and capacitors 22 and 20, aspreviously described. Thus, if the node 132 has been fully charged tothe high negative voltage (14 volts), no current flows through thefield-effect transistor 146 during the subsequent (b clock pulse, whente node 144 is temporarily at the driving voltage of 24 volts (forexample, as depicted by line B in FIG. 2C for the node 24). This stateis indicated by the continuation of line W at the right and left of FIG.2H.

However, if the node 132 is at the low voltage of 4 volts, a substantialcurrent flows through the fieldeffect transistor 146 during thesubsequent (b clock pulse, thereby partially discharging the node 144,and transferring approximately half of the charge difference to the node132. This charge equalization or dumping from 24 V. to 4V. is indicatedby line AA in FIG. 2H, and is precisely the same as previously discussedfor the various stages of the first register 6 (for example line J inFIG. 2C or G in FIG. 2D). In this manner, the data previously containedat the node 132 is transferred to the node 144 during the b clock pulse,and the node 132 has also been brought to the reference voltage of -14volts after (15 in both cases (line W and line A-A to U in FIG. 2H) inpreparation for the next conditional discharge cycle during the nextoccurrence of (11,.

To review the operation of the charge refresh amplifier 9, incombination with the prior cell of the input shift register 6, assumefirst that the node 34 is at the low negative voltage of 4 volts at theend of a (it, pulse (line E in FIG. 2D), signifying that a binary 1"data bit is then present at the node 34 for transfer to the output node24 during the next 4: pulse. At that time (prior to 4%), the output node24 is invariably at the reference voltage of l4 volts (line K or A inFIG. 2C), as described in Section B.

During the next (b clock pulse, the coupling capacitor 22 boosts thenode 24 to 24 volts (line B, FIG. 2C) and the field-effect transistor 26turns ON. Current then flows through the field-effect transistor 26 andcharges the node 34 up to -14 volts (line G, FIG. 2D) and discharges thenode 24 to l4 volts (line F, FIG. 2C). At the end of the 11: clockpulse, the capacitor 22 changes the voltage of the node 24 to 4 volts(line I, FIG. 2C). In this way, the binary l data bit has beentransferred from the node 34 to the output node 24 after 4%.

Following the termination of the d), pulse, the capacitor 120, which isinvariably precharged to l4 volts through the field-effect transistor118 during the (6 clock pulse, is not discharged through thefield-effect transistor 116 to the now-grounded clock bus 12. Since thenode 24 is at 4 volts in this example (binary l transfer), thefieldeffect transistor 116 if OFF and the'capacitor 120 remains chargedto l4 volts.

Some time after the termination of the Q52 clock pulse but before thebeginning of the next :1), clock pulse, the 4),, clock pulse of 20 voltsattempts to turn ON the field-effect transistor 128. However, thegate-to-source voltage (-20 vs. l4 volts) is not sufficient to turn thetransistor 128 ON, and that transistor fails to connect the transistor 116 to the following node 132. The node 132 was previously charged in allcases to the reference l4 volts, as indicated by lines W or A-A in FIG.2H.

In this case, 1 output from the register 6, the node 132 remains fullycharged to l4 volts as indicated by line U, since the conditionaldischarge field-effect transistor 116 is OFF.

The l4 volt charge on the node 132 indicates the binary 1 output fromthe node 24, and the register 6. As previously noted, each outputcircuit 8 inverts the data signal, and an even number of output circuitswill result in no net signal inversion.

When the d), clock pulse ends, the field-effect transistor 128 is heldOFF and the node 132 is thus isolated from the conditional dischargefield-effect transistor 116 during the remainder of the cycle.

The following (I), clock pulse is coupled through the capacitor 136 andboosts the node 132 from l4 volts to 24 volts, as indicated by line V inFIG. 2H; consequently, no significant amount of current flows throughthe field-effect transistor 140 since inadequate gate-tosource voltageis available to turn that transistor ON. At the end of the 4:, clockpulse, the capacitor 136 changes the node 132 back to -14 volts (lineW). Consequently, a binary 1 bit at the node 24 has been inverted andinserted into the node 132; and has then been erased from the node 24.The voltage at node 24 is replenished during d), in this case (1transfer), by the charge-input circuit 13 restoring the node 24 to l4volts as previously described and as indicated by line .l in FIG. 2C.

At the beginning of the next 42 pulse, the coupling capacitor 148 booststhe node 144 from l4 volts to -24 volts. Since the node 132 is at 'l4volts in this example (line W), no current flows through the fieldeffecttransistor 146. Consequently, at the end of the (1) clock pulse, thecapacitor 148 simply changes the node ing register 6, the descriptionstarts at the point where the node 34 is at the high negative voltage, 14 volts, at the end of the (15, pulse (line C in FIG. 2D). Thisindicates that a binary 0 bit is present at the node 34, for transfer tonode 24 during the next 115 pulse. In this case, the coupling capacitor22 boosts the node 24 to 24 volts (line B, FIG. 2C), but the transistor26 remains OFF due to the high negative voltage applied to the source 32by the node 34. There is no charge transfer from the node 24 to the node34 during 4);, and

the node 24 merely reverts to l4 volts after (11 (line D, FlG. 2C),indicating that a "0" has been transferred to the output node 24.

During the capacitor 120 is again precharged to l4 volts through thetransistor 118; however, during this cycle, it discharges to ground ofthe clock bus 12 after 45 since the conditional discharge transistor 116remains ON, indicating that a binary 0 (14 I volts) is then present atthe node 24 after qb After this, the next clock pulse turns ON thefieldeffect transistor. 128, and the node 132 is also discharged throughthe now ON field-effect transistors 128 and 116 to the still-grounded(1) clock bus 12, as indicated by line T in FIG. 2H. Then, the (11.,clock pulse ends and the field-effect transistor 128 turns OFF anddisconnects the node 132 (which is now at ground voltage) from the stillON field-effect transistor 116.

At the beginning of the next 42, clock pulse, the coupling capacitor 136boosts the node 132 to 10 volts (line X) and then, during the 4), clockpulse, the fieldeffect transistor 140 turns ON to correct the voltage ofthe node 132 to l4 volts (line Y). At the end of the d), clock pulse,the capacitor 136 reduces the node 132 to 4 volts (line Z). Therefore,the binary 0 condition on the node 24 has been inverted and transferredto the node 132.

At the start of the next 4: clock pulse, the capacitor 148 invariablychanges the node 144 to 24 volts as previously described. During the (bclock pulse, the field-effect transistor 146 conducts current andcharges the node 132 to -14 volts while discharging the node 144 to l4volts in the usual manner. At the end of the clock pulse, the capacitor148 changes the node 144 from 14 volts to 4 volts, and the inverted 0"output from the register 6 has thus been transferred from the node 132to the first intercell node 144 of the second register 6.

As previously stated, the refresh amplifier 9 together with the outputamplifier 8 couples one shift register to another. Any number of suchcouplings can be made in order to link together a long chain of shiftregisters. Such a long chain would be capable of storing hundreds oreven thousands of bits of information. These hundreds or thousands ofbits are then available one at a time at the output stage 8 of the lastshift register of the chain which can be called a final output.Alternatively, more extensive final output circuits can be employed suchas shown in the copending application of Richard H. Heeren, Ser. No.252,682 filed on even date herewith.

The final output of such a chain of shift registers can be used to drivea cathode ray tube, as illustrated in the prior art. The final output ofa chain of shift registers can also be delivered to the input of thefirst shift register in the chain in order to form the shift registerchain into a recirculating memory. A recirculating memory can be used asa refresh amplifier for a cathode ray tube display.

E ALTERNATE INPUT CIRCUIT In the event that the third phase (4) clockpulse shown in FIG. 1 is unavailable, or does not occur at the optimummoment with respect to the input data signal (7 in FIG. 1), analternative data input circuit is shown in FIG. 3. In this embodiment,the input terminal 70, extending from the source 68 of the inputtransistor 64, is connected to the d), clock bus conductor 10.Therefore, at all times other than during the clock pulse, the terminal70 is grounded or at zero voltage. Alternatively the terminal 70 can beconnected to ground potential provided that the field-effect transistor64 is kept off during the 4), clock pulse in order to prevent prematuredischarge of the node 54. Therefore, if the gate input terminal 72 ofthe transistor 64 is selectively raised to substantially the negativeclock voltage, perhaps less the threshold voltage, at the proper time,the node 54 can selectively be discharged to ground or zero voltage aspreviously described in Section C.

Certain terminals of the circuit 190 are referred to by the referencenumbers 10 and 12'. The terminals 10 are connected to the clock busconductor 10, and the terminals 12 'are connected to the clock busconductor During the (b clock pulse, a field-effect transistor 191 turnsON and thus grounds a capacitor 194 connected to a node 192 which isconnected to the tenninal 72 and thus to the gate of the field-effecttransistor 64. This provides ground or zero voltage on the gate of thefield-effect transistor 64 at the beginning of the next d), pulse.Therefore, the node 54 will not then be discharged after the next d),clock pulse unless the capacitor 194 is immediately recharged to anegative voltage sufficient to turn the transistor 64 ON.

To turn the transistor 64 ON after the next pulse whenever a binary 1"is to be entered into the shift register 6, a field-effect transistor196 connected between the node 192 and the (b, clock conductor and triesto recharge the capacitor 194 to a substantial negative voltage duringthe next and each succeeding d), pulse. If the field-effect transistor196 succeeds in charging the capacitor 194 to a substantial negativevoltage during the 4), pulse, the field-effect transistor 64 will thendischarge the node 54 after the end of the dz, clock pulse, therebyentering a binary 1 signal into the node 54.

However, a field-effect transistor 198 can prevent the field-effecttransistor 196 from recharging the capacitor 194. This is accomplishedwith a voltage divider effect between the negative voltage of the 4),pulse and the grounded (b clock bus terminal 12. The fieldeffecttransistor 198 is constructed so as to be approximately twenty times asconductive as the field-effect transistor 196. Therefore, if thefield-effect transistor 198 is turned ON, only a voltage less than thethreshold voltage of the input field-effect transistor 64 can be appliedto the capacitor 194. The field-effect transistor 198 is selectivelyturned ON by a large negative voltage applied to its gate and is turnedOFF by a negligible or near-ground voltage applied to its gate.

During the (1) clock pulse, a capacitor 200, connected to the gate ofthe field-effect transistor 198, is discharged through a field-effecttransistor 202. Therefore, the field-effect transistor 198 is held inthe OFF condition unless, during the subsequent (1) pulse, a negativeinput voltage is applied to the drain 204 of a field-effect transistor206. A substantial negative voltage (for example, -20 volts, the clockvoltage, or l4 volts, the clock voltage less the threshold) isselectively applied during 4), from a Data Input source 207 to an inputterminal 208 of the input circuit 190, whenever a binary is to beentered into the shift register 6. The input terminal 208 is connectedto the drain 204 of the field-effect transistor 206 so that, during the(b clock pulse, the negative voltage from the data input source 207 mayrecharge the capacitor 200 to a negative voltage and turn on thefield-effect transistor 198. This holds the node 192 at substantiallyground potential and thus enters a binary 0 state signal into the shiftregister 6 by keeping the field-effect transistor 64 OFF.

However, when a negligible or near ground voltage is applied by the datainput source 207 to the input terminal 208 during the d), clock pulse,the gate of the fieldeffect transistor 198 is held at ground potentialduring the 42, clock pulse, keeping the field-effect transistor 198 OFF.The field-effect transistor 196 is then able to charge the capacitor 194to a significant negative voltage in order to turn ON the inputfield-effect transistor 64 and thus discharge the node 54.

In the operation of the alternate input circuit 190, the 4: clock pulsedischarges the capacitor 194 to the now grounded qS clock bus 10 throughthe field-effect transistor 191. At the same time, the capacitor 200 issimilarly discharged to ground potential through the fieldeffecttransistor 202.

During the subsequent clock pulse, the node 54 is invariably charged tol4 volts (the clock voltage less the threshold) as previously describedin Section C. At the same time, the field-effect transistor 196 tries tocharge the capacitor 194 to 14 volts. The node 54 cannot yet bedischarged; because, the terminal is connected to the d), clock and isnow at -20 volts.

If the input terminal 208 carries a substantial negative voltage (binary0"), the capacitor 200 is charge during the tb, clock pulse, and thefield-effect transistor 198 is ON. Conduction by the field-effecttransistor 198 shunts the capacitor 194 to the now-grounded clockterminal 12 and prevents the d), clock signal from charging thecapacitor 194 through the transistor 196. After the termination of theclock pulse, the field-effect transistor 206 decouples the inputterminal 208 from the field-effect transistor 198. Consequently, thecapacitor 194 remains discharged and the input transistor 64 thusremains OFF, causing the node 54 to remain charged to the 0 representingcharge of l4 volts.

Alternatively, if the input terminal 208 carries substantially groundvoltage (binary 1" to be entered), the capacitor 200 cannot benegatively charged from the terminal 208, but stays discharged, and thefieldeffect transistor 198 remains OFF. The field-effect transistor 196then succeeds in charging the capacitor 94 to a substantial negativevoltage during the d), clock pulse. Therefore, the field-effecttransistor 64 tends to be turned ON in this case. After the b, clockpulse ends, the terminal 70, which is connected to the d), clock bus 10,is grounded. Consequently, the field effect transistor 64 is turned ONand the node 54 is discharged through the ON field-effect transistor 64to the grounded terminal 70.

Thus, the alternate input circuit 190 of FIG. 3, serves to discharge theshift-register input node 54 to ground whenever a 1 is desired to beinserted, immediately after the end of the qb, clock pulse, rather thanby using a separate 5 clock pulse after (12 as in the FIG. 1 embodiment.However, the transistor (FIG. 1) and coupling capacitor 60 serve tooptimally adjust the input voltage at the node 54 during (b, in bothembodiments.

While various specific embodiments and examples of the invention havebeen described in detail above, it will be obvious that variousmodifications may be made from the specific details described, withoutdeparting from the spirit and scope of the invention.

What is claimed is:

1. An improved data shifting and storage circuit having a plurality ofstorage devices each having substantially the same storage capacity andserially interconnected by gating devices and coupled to first andsecond clock conductors, wherein the improvement comprises an inputcircuit comprising:

a first gating device having a control electrode and a first controlledelectrode and a second controlled electrode, the control electrode beingconnected to the first clock conductor and the second controlledelectrode connected to one of said storage devices;

a second gating device having a control electrode and a first controlledelectrode and a second controlled electrode, the control electrode andthe first controlled electrode being connected to the second clockconductor and the second controlled electrode being connected to thefirst controlled electrode of the first gating device;

an input storage device having a capacity substantially equal to thecapacity of said storage devices, the input storage device beingconnected between the second clock conductor and the second controlledelectrode of the second gating device; and

third gating device having a control electrode and a first controlledelectrode and a second controlled electrode, the first controlledelectrode being connected to the first controlled electrode of the firstgating device, the control electrode being connected to a first terminaland the second controlled electrode being connected to a secondterminal.

2. A combination according to claim 1 wherein the second terminal isconnected to a conductor capable of assuming either of at least twovoltages.

3. A combination according to claim 1 further comprising a data inputterminal connected to the second terminal.

4. A combination according to claim 3 further comprising: a third clockconductor connected to the first terminal.

5. A combination according to claim 1 wherein the second terminal isconnected to the first clock conductor.

6. A combination according to claim 5 further comprising a data inputcircuit connected to the first terminal.

7. A combination according to claim 1 further comprising an inputterminal and wherein the second terminal is connected to the inputterminal.

8. A data input circuit for a charge-transfer multivoltage type memorywherein the several stages of the memory include charge stores of equalmagnitude, wherein a charge is transferred from stage to stage throughthe several stages, each charge store for storing at least two differentstates of data-representing charge voltage comprising:

an input charge store of magnitude substantially no more than themagnitude of the charge stores of each of the several stages;

means responsive to data signals for selectively discharging the chargeof the input charge store to a voltage substantially beyond a rangedefined by the two states of data-representing charge voltage; and

means operative after the selectively discharging means for rechargingthe input charge store to exactly the voltage of one of the two statesof datarepresenting charge voltage. 9. A circuit according to claim 8wherein the recharging means comprises: a switching device forconnecting the input charge store to a reference voltage after eachoperation of the discharging means.

10. A circuit according to claim 8 wherein the discharging meanscomprises a switching device for periodically connecting the inputcharge store to a selectively controlled discharge terminal.

11. A circuit according to claim 10 wherein the switching device isoperated after each charge-transfer operation.

12. A circuit according to claim 8 wherein the discharging meanscomprises a switching device for selectively connecting the input chargestore to a discharge terminal.

13. A circuit according to claim 12 comprising means for selectivelyoperating the switching device after each charge-transfer operation.

14. A circuit according to claim 13 wherein the selectively operatingmeans comprises: means for generating a timing signal after each chargetransfer operation; and means responsive to input data signals gatingthe timing signal to the switching device.

15. A method of delivery of data to a charge-transfertype shift registerhaving charge storage elements in each stage which store binary databits at either of two distinct voltage levels, gating devices fortransferring charge sequentially from charge storage element to chargestorage element, and a separate input charge storage element comprising:I

substantially matching the capacity of the input storage element to thestorage elements of the several stages;

discharging the input storage element of the input stage of the registerto a voltage beyond a range defined by the two voltages; and

recharging the charge voltage on the input storage element to one ofsaid two voltage levels.

16. A method of delivering data to a charge-transfertype circuit whereindata are stored on charge storage devices having two data-representingvoltage states and wherein charge is transferred from charge storagedevice to charge storage device by gating devices wherein the circuithas at least an input stage, comprising:

selectively discharging the storage element of the input stage of theregister to a voltage outside of a range defined by said two voltages;and correcting the charge on the storage element of the input stage toone of the two voltages.

1. An Improved data shifting and storage circuit having a plurality ofstorage devices each having substantially the same storage capacity andserially interconnected by gating devices and coupled to first andsecond clock conductors, wherein the improvement comprises an inputcircuit comprising: a first gating device having a control electrode anda first controlled electrode and a second controlled electrode, thecontrol electrode being connected to the first clock conductor and thesecond controlled electrode connected to one of said storage devices; asecond gating device having a control electrode and a first controlledelectrode and a second controlled electrode, the control electrode andthe first controlled electrode being connected to the second clockconductor and the second controlled electrode being connected to thefirst controlled electrode of the first gating device; an input storagedevice having a capacity substantially equal to the capacity of saidstorage devices, the input storage device being connected between thesecond clock conductor and the second controlled electrode of the secondgating device; and a third gating device having a control electrode anda first controlled electrode and a second controlled electrode, thefirst controlled electrode being connected to the first controlledelectrode of the first gating device, the control electrode beingconnected to a first terminal and the second controlled electrode beingconnected to a second terminal.
 2. A combination according to claim 1wherein the second terminal is connected to a conductor capable ofassuming either of at least two voltages.
 3. A combination according toclaim 1 further comprising a data input terminal connected to the secondterminal.
 4. A combination according to claim 3 further comprising: athird clock conductor connected to the first terminal.
 5. A combinationaccording to claim 1 wherein the second terminal is connected to thefirst clock conductor.
 6. A combination according to claim 5 furthercomprising a data input circuit connected to the first terminal.
 7. Acombination according to claim 1 further comprising an input terminaland wherein the second terminal is connected to the input terminal.
 8. Adata input circuit for a charge-transfer multivoltage type memorywherein the several stages of the memory include charge stores of equalmagnitude, wherein a charge is transferred from stage to stage throughthe several stages, each charge store for storing at least two differentstates of data-representing charge voltage comprising: an input chargestore of magnitude substantially no more than the magnitude of thecharge stores of each of the several stages; means responsive to datasignals for selectively discharging the charge of the input charge storeto a voltage substantially beyond a range defined by the two states ofdata-representing charge voltage; and means operative after theselectively discharging means for recharging the input charge store toexactly the voltage of one of the two states of data-representing chargevoltage.
 9. A circuit according to claim 8 wherein the recharging meanscomprises: a switching device for connecting the input charge store to areference voltage after each operation of the discharging means.
 10. Acircuit according to claim 8 wherein the discharging means comprises aswitching device for periodically connecting the input charge store to aselectively controlled discharge terminal.
 11. A circuit according toclaim 10 wherein the switching device is operated after eachcharge-transfer operation.
 12. A circuit according to claim 8 whereinthe discharging means comprises a switching device for selectivelyconnecting the input charge store to a discharge terminal.
 13. A circuitaccording to claim 12 comprising means for selectively operating theswitching device after each charge-transfer operation.
 14. A circuitaccording to claim 13 wherein the selectively operating Means comprises:means for generating a timing signal after each charge transferoperation; and means responsive to input data signals gating the timingsignal to the switching device.
 15. A method of delivery of data to acharge-transfer-type shift register having charge storage elements ineach stage which store binary data bits at either of two distinctvoltage levels, gating devices for transferring charge sequentially fromcharge storage element to charge storage element, and a separate inputcharge storage element comprising: substantially matching the capacityof the input storage element to the storage elements of the severalstages; discharging the input storage element of the input stage of theregister to a voltage beyond a range defined by the two voltages; andrecharging the charge voltage on the input storage element to one ofsaid two voltage levels.
 16. A method of delivering data to acharge-transfer-type circuit wherein data are stored on charge storagedevices having two data-representing voltage states and wherein chargeis transferred from charge storage device to charge storage device bygating devices wherein the circuit has at least an input stage,comprising: selectively discharging the storage element of the inputstage of the register to a voltage outside of a range defined by saidtwo voltages; and correcting the charge on the storage element of theinput stage to one of the two voltages.